1. Field of the Invention
This invention relates to a semiconductor device prepared by use of a semiconductor layer formed on an insulating substrate.
2. Description of the Prior Art
Thin film semiconductor devices of the prior art having a semiconductor (e.g. silicon) layer provided on an insulating substrate have the advantages of easy isolation (i.e. separation between elements) and small floating capacitance, as compared with devices using a silicon crystal as the substrate.
While the SOS (Silicon on Sapphire) technique has the above-mentioned advantages, there is involved a problem that the product cost is relatively high, because sapphire employed for the substrate is expensive. Further, the preparation of MOS type transistors according to the SOS technique, which employs the silicon planar step of the prior art, poses a problem that no device can be prepared without passing through high temperature steps such as oxidation, diffusion, ion implantation, annealing, etc.
Accordingly, wiring for the electrodes in preparation of the device is generally practiced all on the top part of the insulating layer, after having passed through the high temperature fabrication steps. Further, in the SOS technique, when employing for example a crystalline silicon for the semiconductor layer, unless the semiconductor layer has a layer thickness of about 1.mu. at least, no satisfactory crystalline silicon film can be obtained on the substrate surface. For this reason, in wiring for electrodes on the top part of the insulating layer, it is required to prevent leaks arising in a thin part of the insulating layer resulting from the level difference between the substrate and the source region or the drain region.
Thus, the insulating layer or the metal film for wiring is required to be made thicker so that no leak or wire disconnection may occur. Instead, it has been also proposed to make the semiconductor layer or other layers tapered in the isolation fabrication step or to carry out partial oxidation, etc. to make the level difference moderate or substantially decrease the level difference. However, use of the latter approach will also lead to the problem that the preparation of the semiconductor device become complicated. Also, when the insulating layer is made thicker than is necessary, there may ensue the problem that it may have sometimes adverse effects on the characteristics of the semiconductor device.
Besides, according to the method of the prior art, wiring is effected on the top part of the element by perforating contact holes through the insulating layer. Since such a method requires specific area for contact holes on the top part of the semiconductor device, there has been the problem that the degree of integration of the semiconductor is somewhat restricted. Further, excessive wiring on the top part of the device will require more fabrication steps for preventing short-circuiting between wirings.